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VHDL Courses in PDF |
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Basic Level, 70% Lecture, 30% Labs
This two-day fast-track primer course in VHDL is recommended for the broader corporate audience including application engineers, R&D personnel, hotline engineers, technical writers, and engineering managers. People whose role demands the ability to read VHDL code, understand VHDL-specific issues, identify inefficient or non-synthesizable constructs, and support those who write code will benefit from this course. Both synthesis and simulation aspects of the language are covered. Practical lab exercises provide course participants with direct insight into how the capabilities of the language are used to develop and verify complex ICs, using today's EDA tools.
Basic Level, 50% Lecture, 50% Labs
VHDL is a feature-rich hardware description language, well suited to the synthesis and verification of complex system-on-a-chip ASICs and FPGAs. This course, is a hardware-oriented VHDL primer for the digital design or verification engineer. Through real-world lecture insights and lab examples, participants in this comprehensive, hands-on course will learn to write synthesis-friendly, simulator-efficient code for progressively more complex logic blocks. They'll acquire confidence in utilizing the more powerful aspects of the language, while gaining mastery over its intricacies. The course focuses 70% on RTL code for synthesis, and 30% on testbench code for simulation.
For Synthesis & Verification
Advanced Level, 50% Lecture, 50% Labs Synthesis and verification are key to successful ASIC and FPGA design. This course addresses a wide range of VHDL design areas integral to the design process. The course explores, in a tool independent format, methodology issues and examples, VHDL coding and modeling guidelines for synthesizable design and design verification. Lecture sessions are supported by multiple VHDL examples for each topic and are reinforced by application specific labs. Additional topics include creating synthesizable code for control, datapath, and FSM oriented designs. Creating verification environments and testbenches of varying complexity are fully explained. Additional topics include VHDL commenting guidelines, effective use of VHDL data types, and design for reuse issues.
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Tom Wille
TM Associates, Inc.
14420 S. Kelmsley Dr.
Oregon City, OR 97045
503-656-4457
503-656-4775 fax
tw@tm-associates.com
© 2006, TM Associates, Inc.