Lattice FPGAs with Verilog

Overview
Verilog is widely used in the design and verification of platform FPGAs. This three-day course will familiarize you with key language features in the context of real-world FPGA development. The course focuses on Lattice FPGA implementation tools and technology.

If you’ve had some on-the-job exposure to Verilog, these lectures and labs will fill in the gaps, and show you how to write synthesis-efficient code. If you’re already familiar with Verilog-95, you’ll gain exposure to the many enhancements provided by Verilog-01 (IEEE Std 1364-2001).
 
You’ll describe and revise synthesizable Verilog modules, then take them through mapping and routing. You’ll also write testbench code to verify functionality. You’ll learn coding techniques to enhance device performance or resource utilization.

Benefits
Upon completion of this course, students will:

• Know what Verilog constructs to use in various coding scenarios
• Understand nuances of syntax and semantics for both synthesis and simulation
• Envision the synthesized logic expected from the HDL code.
• Take designs through the entire Lattice FPGA implementation flow
• Use Lattice features like clock constraints, floorplan groups, and pad preferences
• Write Verilog code to meet timing or utilization constraints

Intended Audience
Design and verification engineers whose knowledge of Verilog ranges from some on-the-job exposure to little or none, and who want to sharpen their skill set. Engineers who want to spin up on designing with Lattice tools and technology, in a Verilog environment, would also benefit. The course is also useful for test engineers who want to write Verilog patterns, product engineers who want to understand source code, and technical managers. 

For a more comprehensive, syntax-oriented introduction to all aspects of the Verilog language, we recommend the four-day Verilog for Hardware Designers, in which you’ll code, simulate and synthesize design examples in a variety of IC technologies.

Prerequisites
Students should be familiar with digital design principles and programming language concepts.

Suggested follow-on course:
Advanced Verilog 2001 Coding Styles for Synthesis & Verification

Training Approach
This is an intensive, interactive course, which is approximately 50% lecture and 50% lab.  Questions are highly encouraged. 

Course Outline

Day 1:

Verilog Design Flow with ispLEVER

• How HDLs Work
• Simulation and synthesis tools
• Lattice FPGA imlementation tools
• FPGA flow, Verilog code to bit file

Elements of Verilog Syntax

• Lexical conventions
• Literal Bit Vectors
• Data Types: Variables vs Nets
• Assignments and Expressions
• Parameters: Symbolic Names

Lab Exercises

Verilog Operators

• Concatenate and Replicate
• Bitwise Operators
• Arithmetic Operators
• Shift and Rotate Operations
• Precedence of Operators

Lab Exercises

Dataflow Coding

• Anatomy of continuous assign
• Describing glue logic
• More complex dataflow code

Lab Exercises

Day 2:

Structural Verilog Coding 

• Instantiating submodules
• Using Lattice IPexpress
• Data types for declaring ports
• Probing via hierarchical pathnames

Lab Exercises

Writing and Running Testbenches

• Code a classic testbench
• Instantiate a design under verification
• Hooking up stub signals
• Effective stimulus generation code
• Monitoring response via waveforms or tabular data
• Event-driven simulation

Lab Exercises

RTL Coding for Combinational Logic

• Algorithmic description of hardware
• Anatomy of an always construct
• Controlling execution of algorithms
• Nuances of if-else, case(z), for, while
• Understanding priority in if-else and case

Lab Exercises

RTL Coding for Sequential Logic

• Level Sensitive Code
• Edge Triggered Code
• Nonblocking Syntax
• Resets (asynchronous vs. synchronous)

Lab Exercises

Day 3:

Enhancing Performance

• Constraining the Clock
• Controlling Clock Enables
• Prioritizing Reset, Enable
• Using IO FFs
• Coding for Speed
• Global Set-Reset
• Controlling Fanout

Lab Exercises

Fine Tuning FPGA Device

• Speed Grades
• I/O Placement
• Hold Time Constraints
• Floorplanning Groups
• Timing Closure Strategies

Lab Exercises

Using HDL Explorer

• Syntax-Checking and linting code
• Using Design Review
• Examining Design Connectivity
• HDL Guidelines at a Glance